Hybrid CMOS-MQCA Logic Architectures using Multi-Layer Spintronic Devices

Jayita Das; Syed M. Alam; Srinath Rajaram; Sanjukta Bhanja

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arXiv · 1102.4034

Hybrid CMOS-MQCA Logic Architectures using Multi-Layer Spintronic Devices

Jayita Das·Syed M. Alam·Srinath Rajaram·Sanjukta Bhanja

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Abstract

We present a novel hybrid CMOS-MQCA architecture using multi-layer Spintronic devices as computing elements. A feasibility study is presented with 22nm CMOS where new approaches for spin transfer torque induced clocking and read-out scheme for variability-tolerance are introduced. A first-of-its-kind Spintronic device model enables circuit simulation using existing CAD infrastructure. Approximately 70% reduction in energy consumption is observed when compared against conventional field-induced clocking scheme.

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BibTeX RIS

Jayita Das, Syed M. Alam, Srinath Rajaram, Sanjukta Bhanja. 2012-03-17. Hybrid CMOS-MQCA Logic Architectures using Multi-Layer Spintronic Devices. https://arxiv.org/abs/1102.4034

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