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arXiv · 1301.4779

Formal Verification of Hardware Synthesis

Thomas Braibant·Adam Chlipala
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Abstract

We report on the implementation of a certified compiler for a high-level hardware description language (HDL) called Fe-Si (FEatherweight SynthesIs). Fe-Si is a simplified version of Bluespec, an HDL based on a notion of guarded atomic actions. Fe-Si is defined as a dependently typed deep embedding in Coq. The target language of the compiler corresponds to a synthesisable subset of Verilog or VHDL. A key aspect of our approach is that input programs to the compiler can be defined and proved correct inside Coq. Then, we use extraction and a Verilog back-end (written in OCaml) to get a certified version of a hardware design.

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Thomas Braibant, Adam Chlipala. 2013-01-21. Formal Verification of Hardware Synthesis. https://doi.org/10.1007/978-3-642-39799-8_14

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