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arXiv · 1405.0413

Multiplierless Approximate 4-point DCT VLSI Architectures for Transform Block Coding

F. M. Bayer·R. J. Cintra·A. Madanayake·U. S. Potluri
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Abstract

Two multiplierless algorithms are proposed for 4x4 approximate-DCT for transform coding in digital video. Computational architectures for 1-D/2-D realisations are implemented using Xilinx FPGA devices. CMOS synthesis at the 45 nm node indicate real-time operation at 1 GHz yielding 4x4 block rates of 125 MHz at less than 120 mW of dynamic power consumption.

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F. M. Bayer, R. J. Cintra, A. Madanayake, U. S. Potluri. 2014-05-02. Multiplierless Approximate 4-point DCT VLSI Architectures for Transform Block Coding. https://doi.org/10.1049/el.2013.1352

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