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arXiv · 1412.6043

A 237 Gbps Unrolled Hardware Polar Decoder

Pascal Giard·Gabi Sarkis·Claude Thibeault·Warren J. Gross
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Abstract

In this letter we present a new architecture for a polar decoder using a reduced complexity successive cancellation decoding algorithm. This novel fully-unrolled, deeply-pipelined architecture is capable of achieving a coded throughput of over 237 Gbps for a (1024,512) polar code implemented using an FPGA. This decoder is two orders of magnitude faster than state-of-the-art polar decoders.

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Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross. 2014-12-18. A 237 Gbps Unrolled Hardware Polar Decoder. https://doi.org/10.1049/el.2014.4432

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