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arXiv · 1502.04181

Novel Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

Tillmann Krauss·Frank Wessely·Udo Schwalke
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Abstract

In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establish Schottky barrier FET (SBFET) operation and one front-gate forming a junctionless FET (JLFET) for actual current control, significantly increases the temperature robustness of the device.

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Tillmann Krauss, Frank Wessely, Udo Schwalke. 2015-02-14. Novel Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications. https://arxiv.org/abs/1502.04181

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