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arXiv · 1502.07267

Accuracy Enhancement of Pickett Tunnelling Barrier Memristor Model

Abstract

Titanium dioxide (TiO2) memristors exhibit complex conduction mechanism. Several models of different complexity have been developed in order to mimic the experimental results for physical behaviors observed in memristor devices. Pickett's tunneling barrier model describes the TiO2 memristors, and utilizes complex derivative of tunnel barrier width. It attains a large error in the ON switching region. Variety of research consider it as the reference model for the TiO2 memristors. In this paper, we first analyze the theory of operation of the memristor and discuss Pickett's model. Then, we propose a modification to its derivative functions to provide a lower error and closer agreement with physical behavior. This modification is represented by two additional fitting parameters to damp or accelerate the tunnel width derivative. Also, we incorporate a hard limiter term to limit the tunnel width to its physical extremes 1 nm and 2 nm. We run simulations to test the model modifications and we compare the results to the experimental and original Pickett's model results. The modified model more closely resembles the experimental behavior of TiO2 memristors and potentially enables the memristor to be used as a multilevel memory.

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BibTeXRIS

Ahmad Daoud, Ahmed Dessouki, Sherif Abuelenin. 2015-02-25. Accuracy Enhancement of Pickett Tunnelling Barrier Memristor Model. https://doi.org/10.1109/icitacee.2014.7065715

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