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arXiv · 1503.03880

Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations

François Leduc-Primeau·Frank R. Kschischang·Warren J. Gross
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Abstract

This paper proposes a "quasi-synchronous" design approach for signal processing circuits, in which timing violations are permitted, but without the need for a hardware compensation mechanism. The case of a low-density parity-check (LDPC) decoder is studied, and a method for accurately modeling the effect of timing violations at a high level of abstraction is presented. The error-correction performance of code ensembles is then evaluated using density evolution while taking into account the effect of timing faults. Following this, several quasi-synchronous LDPC decoder circuits based on the offset min-sum algorithm are optimized, providing a 23%-40% reduction in energy consumption or energy-delay product, while achieving the same performance and occupying the same area as conventional synchronous circuits.

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François Leduc-Primeau, Frank R. Kschischang, Warren J. Gross. 2015-03-12. Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations. https://arxiv.org/abs/1503.03880

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