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arXiv · 1603.03921

Molecular MIMO: From Theory to Prototype

Abstract

In diffusion-based molecular communication, information transport is governed by diffusion through a fluid medium. The achievable data rates for these channels are very low compared to the radio-based communication system, since diffusion can be a slow process. To improve the data rate, a novel multiple-input multiple-output (MIMO) design for molecular communication is proposed that utilizes multiple molecular emitters at the transmitter and multiple molecular detectors at the receiver (in RF communication these all correspond to antennas). Using particle-based simulators, the channel's impulse response is obtained and mathematically modeled. These models are then used to determine inter-link interference (ILI) and inter-symbol interference (ISI). It is assumed that when the receiver has incomplete information regarding the system and the channel state, low complexity symbol detection methods are preferred since the receiver is small and simple. Thus four detection algorithms are proposed---adaptive thresholding, practical zero forcing with channel models excluding/including the ILI and ISI, and Genie-aided zero forcing. The proposed algorithms are evaluated extensively using numerical and analytical evaluations.

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Bon-Hong Koo, Changmin Lee, H. Birkan Yilmaz, Nariman Farsad, Andrew Eckford, Chan-Byoung Chae. 2016-03-12. Molecular MIMO: From Theory to Prototype. https://doi.org/10.1109/jsac.2016.2525538

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