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arXiv · 1702.05614

A Novel Method of Discrete-Time Amplification using NEMS Devices

Abstract

In this paper we propose a novel method of realizing discrete-time (D-T) signal amplification using Nano-Electro-Mechanical (NEMS) devices. The amplifier uses mechanical devices instead of traditional solid-state circuits. The proposed NEMS-based D-T amplifier provides high gain and operate on a wide dynamic range of signals, consuming only a few micro watts of power. The proposed concept is subsequently verified using Verilog-A model of the NEMS device. Modifications in the proposed amplifier to suit different specifications are also presented.

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BibTeXRIS

Sivaneswaran Sankar, Maryam Shojaei Baghini, Valipe Ramgopal Rao. 2018-05-22. A Novel Method of Discrete-Time Amplification using NEMS Devices. https://doi.org/10.1109/ted.2018.2867547

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