Parasitic Bipolar Leakage in III-V FETs: Impact of Substrate Architecture

Abstract

InGaAs-based Gate-all-Around (GAA) FETs with moderate to high In content are shown experimentally and theoretically to be unsuitable for low-leakage advanced CMOS nodes. The primary cause for this is the large leakage penalty induced by the Parasitic Bipolar Effect (PBE), which is seen to be particularly difficult to remedy in GAA architectures. Experimental evidence of PBE in In70Ga30As GAA FETs is demonstrated, along with a simulation-based analysis of the PBE behavior. The impact of PBE is investigated by simulation for alternative device architectures, such as bulk FinFETs and FinFETs-on-insulator. PBE is found to be non-negligible in all standard InGaAs FET designs. Practical PBE metrics are introduced and the design of a substrate architecture for PBE suppression is elucidated. Finally, it is concluded that the GAA architecture is not suitable for low-leakage InGaAs FETs; a bulk FinFET is better suited for the role.