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arXiv · 1712.03411

FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability

Guanshun Yu·Tom Y. Cheng·Blayne Kettlewell·Harrison Liew·Mingoo Seok·Peter R. Kinget
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Abstract

This paper outlines an FPGA VLSI design methodology that was used to realize a fully functioning FPGA chip in 130nm CMOS with improved routability and memory robustness. The architectural design space exploration and synthesis capability were enabled by the Verilog-to-Routing CAD tool. The capabilities of this tool were extended to enable bitstream generation and deployment. To validate the architecture and bitstream implementation, a Chisel (Constructing Hardware in the Embedded Scala Language) model of the FPGA was created to rapidly verify the microarchitectural details of the device prior to schematic design. A custom carrier board and configuration tool were used to verify correct operational characteristics of the FPGA over various resource utilizations and clock frequencies.

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Guanshun Yu, Tom Y. Cheng, Blayne Kettlewell, Harrison Liew, Mingoo Seok, Peter R. Kinget. 2017-12-09. FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability. https://arxiv.org/abs/1712.03411

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