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arXiv · 1803.01431

Design of a Low Voltage Analog-to-Digital Converter using Voltage Controlled Stochastic Switching of Low Barrier Nanomagnets

Abstract

The inherent stochasticity in many nano-scale devices makes them prospective candidates for low-power computations. Such devices have been demonstrated to exhibit probabilistic switching between two stable states to achieve stochastic behavior. Recently, superparamagnetic nanomagnets (having low energy barrier EB $\sim$ 1kT) have shown promise of achieving stochastic switching at GHz rates, with very low currents. On the other hand, voltage-controlled switching of nanomagnets through the Magneto-electric (ME) effect has shown further improvements in energy efficiency. In this simulation paper, we first analyze the stochastic switching characteristics of such super-paramagnetic nanomagnets in a voltage-controlled spintronic device. We study the influence of external bias on the switching behavior. Subsequently, we show that our proposed device leverages the voltage controlled stochasticity in performing low-voltage 8-bit analog to digital conversions. This eliminates the need for comparators, unlike the Complementary Metal-Oxide Semiconductor (CMOS)-based flash Analog-to-Digital converters (ADC). This device allows for a simple and compact design which can potentially be applied in implementing sensors which desire low voltage conversions.

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Indranil Chakraborty, Amogh Agrawal, Kaushik Roy. 2018-05-23. Design of a Low Voltage Analog-to-Digital Converter using Voltage Controlled Stochastic Switching of Low Barrier Nanomagnets. https://doi.org/10.1109/lmag.2018.2839097

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