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arXiv · 1905.08239

Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture

Jakub Žádník·Jarmo Takala
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Abstract

This paper describes a low-power processor tailored for fast Fourier transform computations where transport triggering template is exploited. The processor is software-programmable while retaining an energy-efficiency comparable to existing fixed-function implementations. The power savings are achieved by compressing the computation kernel into one instruction word. The word is stored in an instruction loop buffer, which is more power-efficient than regular instruction memory storage. The processor supports all power-of-two FFT sizes from 64 to 16384 and given 1 mJ of energy, it can compute 20916 transforms of size 1024.

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Jakub Žádník, Jarmo Takala. 2019-05-18. Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture. https://doi.org/10.1109/icassp.2019.8682289

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