Cryogenic low power CMOS analog buffer at 4.2K

Yajie Huang; Chao Luo; Tengteng Lu; Zhen Li; Jun Xu; Guoping Guo

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arXiv · 1905.09560

Cryogenic low power CMOS analog buffer at 4.2K

Yajie Huang·Chao Luo·Tengteng Lu·Zhen Li·Jun Xu·Guoping Guo

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Abstract

A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18um CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit could achieve a slew-rate of +51 V/us and -93 V/us for 10 pF capacitive load. The static power of the circuit is only 79uW.

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BibTeX RIS

Yajie Huang, Chao Luo, Tengteng Lu, Zhen Li, Jun Xu, Guoping Guo. 2019-05-23. Cryogenic low power CMOS analog buffer at 4.2K. https://arxiv.org/abs/1905.09560

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