Performance Considerations of Thin Ferroelectrics (~10 nm HfO2, ~20 nm PZT) FDSOI NCFETs for Digital Circuits at Reduced Power Consumption

Shruti Mehrotra; S. Qureshi

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arXiv · 1906.05031

Performance Considerations of Thin Ferroelectrics (~10 nm HfO2, ~20 nm PZT) FDSOI NCFETs for Digital Circuits at Reduced Power Consumption

Shruti Mehrotra·S. Qureshi

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Abstract

The paper presents simulation study of thin ferroelectrics (Si doped HfO2, PZT) PGP FDSOI NCFETs at circuit level for high performance, low VDD low-power digital circuits. The baseline PGP FDSOI MOSFET has 20 nm metal gate length with supply voltage varying from 0.5 V to 0.9 V. The circuits studied were 3-stage CMOS ring oscillator, NAND-2 and NOR-2 gates at a frequency of 20 GHz. The paper shows that HfO2 FDSOI NCFET based NAND-2 gates can provide significant reduction in average power consumption, which was ~66% that of baseline FDSOI MOSFET based NAND-2 gates for comparable performance. For the same performance, the average power consumption for PZT FDSOI NCFET based NAND-2 gate was ~86% that of baseline FDSOI MOSFET based NAND-2 gate. The power-delay product of HfO2 FDSOI NCFET based gates was found to be ~24% lower than baseline FDSOI MOSFET based gates and that of PZT FDSOI NCFET based gates was found to be ~21% less than that of baseline FDSOI MOSFET based gates. The performance of HfO2 FDSOI NCFET based gates with increased fan-in and fan-out was also found to be superior to PZT FDSOI NCFET based gates and baseline FDSOI MOSFET based gates.

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Shruti Mehrotra, S. Qureshi. 2019-06-12. Performance Considerations of Thin Ferroelectrics (~10 nm HfO2, ~20 nm PZT) FDSOI NCFETs for Digital Circuits at Reduced Power Consumption. https://arxiv.org/abs/1906.05031

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