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arXiv · 2010.07413

A Novel Quantum Algorithm for Ant Colony Optimization

Abstract

Ant colony optimization (ACO) is a commonly used meta-heuristic to solve complex combinatorial optimization problems like traveling salesman problem (TSP), vehicle routing problem (VRP), etc. However, classical ACO algorithms provide better optimal solutions but do not reduce computation time overhead to a significant extent. Algorithmic speed-up can be achieved by using parallelism offered by quantum computing. Existing quantum algorithms to solve ACO are either quantum-inspired classical algorithms or hybrid quantum-classical algorithms. Since all these algorithms need the intervention of classical computing, leveraging the true potential of quantum computing on real quantum hardware remains a challenge. This paper's main contribution is to propose a fully quantum algorithm to solve ACO, enhancing the quantum information processing toolbox in the fault-tolerant quantum computing (FTQC) era. We have Solved the Single Source Single Destination (SSSD) shortest-path problem using our proposed adaptive quantum circuit for representing dynamic pheromone updating strategy in real IBMQ devices. Our quantum ACO technique can be further used as a quantum ORACLE to solve complex optimization problems in a fully quantum setup with significant speed up upon the availability of more qubits.

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BibTeXRIS

Mrityunjay Ghosh, Nivedita Dey, Debdeep Mitra, Amlan Chakrabarti. 2021-09-04. A Novel Quantum Algorithm for Ant Colony Optimization. https://doi.org/10.1049/qtc2.12023

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