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arXiv · 2107.03234

Quadratic and Higher-Order Unconstrained Binary Optimization of Railway Rescheduling for Quantum Computing

Abstract

As consequences of disruptions in railway traffic affect passenger experience/satisfaction, appropriate rerouting and/or rescheduling is necessary. These problems are known to be NP-hard, given the numerous restrictions of traffic nature. With the recent advances in quantum technologies, quantum annealing has become an alternative method to solve such optimization problems. To use quantum annealing, the problem needs to be encoded in QUBO (quadratic unconstrained binary optimization) or HOBO (higher-order binary optimization) formulation that can be recast as a QUBO. This paper introduces QUBO and HOBO representations for rescheduling problems of railway traffic management; the latter is a new approach up to our knowledge. This new approach takes into account not only the single-track lines but also the double- and multi-track lines, as well as stations composed of tracks and switches. We consider the conditions of minimal headway between trains, minimal stay on stations, track occupation, and rolling stock circulation. Furthermore, a hybrid quantum-classical procedure is presented that includes rerouting. We demonstrate the proof of concept implementation on the D-Wave Quantum Processing Unit and D-Wave hybrid solver.

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Krzysztof Domino, Akash Kundu, Özlem Salehi, Krzysztof Krawiec. 2022-07-20. Quadratic and Higher-Order Unconstrained Binary Optimization of Railway Rescheduling for Quantum Computing. https://doi.org/10.1007/s11128-022-03670-y

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