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arXiv · 2208.08384

Temporal Relaxation of Signal Temporal Logic Specifications for Resilient Control Synthesis

Ali Tevfik Buyukkocak·Derya Aksaray
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Abstract

We introduce a metric that can quantify the temporal relaxation of Signal Temporal Logic (STL) specifications and facilitate resilient control synthesis in the face of infeasibilities. The proposed metric quantifies a cumulative notion of relaxation among the subtasks, and minimizing it yields to structural changes in the original STL specification by i) modifying time-intervals, ii) removing subtasks entirely if needed. To this end, we formulate an optimal control problem that extracts state and input sequences by minimally violating the temporal requirements while achieving the desired predicates. We encode this problem in the form of a computationally efficient mixed-integer program. We show some theoretical results on the properties of the new metric. Finally, we present a case study of a robot that minimally violates the time constraints of desired tasks in the face of an infeasibility.

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Ali Tevfik Buyukkocak, Derya Aksaray. 2022-12-11. Temporal Relaxation of Signal Temporal Logic Specifications for Resilient Control Synthesis. https://arxiv.org/abs/2208.08384

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