An Algorithm-Hardware Co-design Framework to Overcome Imperfections of Mixed-signal DNN Accelerators

Abstract

In recent years, processing in memory (PIM) based mixedsignal designs have been proposed as energy- and area-efficient solutions with ultra high throughput to accelerate DNN computations. However, PIM designs are sensitive to imperfections such as noise, weight and conductance variations that substantially degrade the DNN accuracy. To address this issue, we propose a novel algorithm-hardware co-design framework hereafter referred to as HybridAC that simultaneously avoids accuracy degradation due to imperfections, improves area utilization, and reduces data movement and energy dissipation. We derive a data-movement-aware weight selection method that does not require retraining to preserve its original performance. It computes a fraction of the results with a small number of variation-sensitive weights using a robust digital accelerator, while the main computation is performed in analog PIM units. This is the first work that not only provides a variation-robust architecture, but also improves the area, power, and energy of the existing designs considerably. HybridAC is adapted to leverage the preceding weight selection method by reducing ADC precision, peripheral circuitry, and hybrid quantization to optimize the design. Our comprehensive experiments show that, even in the presence of variation as high as 50%, HybridAC can reduce the accuracy degradation from 60 - 90% (without protection) to 1 - 2% for different DNNs across diverse datasets. In addition to providing more robust computation, compared to the ISAAC (SRE), HybridAC improves the execution time, energy, area, power, area-efficiency, and power-efficiency by 26%(14%), 52%(40%), 28%(28%), 57%(45%), 43%(5x), and 81%(3.9x), respectively