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arXiv · 2211.12239

Photonic Spiking Neural Networks with Highly Efficient Training Protocols for Ultrafast Neuromorphic Computing Systems

Abstract

Photonic technologies offer great prospects for novel ultrafast, energy-efficient and hardware-friendly neuromorphic (brain-like) computing platforms. Moreover, neuromorphic photonic approaches based upon ubiquitous, technology-mature and low-cost Vertical-Cavity Surface Emitting Lasers (VCSELs) (devices found in fibre-optic transmitters, mobile phones, automotive sensors, etc.) are of particular interest. Given VCSELs have shown the ability to realise neuronal optical spiking responses (at ultrafast GHz rates), their use for spike-based information processing systems has been proposed. In this work, Spiking Neural Network (SNN) operation, based on a hardware-friendly photonic system of just one Vertical Cavity Surface Emitting Laser (VCSEL), is reported alongside a novel binary weight 'significance' training scheme that fully capitalises on the discrete nature of the optical spikes used by the SNN to process input information. The VCSEL-based photonic SNN is tested with a highly complex, multivariate, classification task (MADELON) before performance is compared using a traditional least-squares training method and the alternative novel binary weighting scheme. Excellent classification accuracies of >94% are reached by both training methods, exceeding the benchmark performance of the dataset in a fraction of processing time. The newly reported training scheme also dramatically reduces training set size requirements as well as the number of trained nodes (<1% of the total network node count). This VCSEL-based photonic SNN, in combination with the reported 'significance' weighting scheme, therefore grants ultrafast spike-based optical processing with highly reduced training requirements and hardware complexity for potential application in future neuromorphic systems and artificial intelligence applications.

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BibTeXRIS

Dafydd Owen-Newns, Joshua Robertson, Matej Hejda, Antonio Hurtado. 2022-11-22. Photonic Spiking Neural Networks with Highly Efficient Training Protocols for Ultrafast Neuromorphic Computing Systems. https://arxiv.org/abs/2211.12239

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