Search arXiv⌕ Search
Home/Archive/arXiv

arXiv · 2306.13721

Enhanced Read Resolution in Reconfigurable Memristive Synapses for Spiking Neural Networks

Hritom Das·Nishith N. Chakraborty·Catherine Schuman·Garrett S. Rose
View original source ↗Read source document ↗Export metadata ↓

Abstract

Synapse is a key element of any neuromorphic computing system which is mostly constructed with memristor devices. A memristor is a two-terminal analog memory device. Memristive synapse suffers from various challenges such as forming at high voltage, SET, RESET failure, and READ margin or resolution issue between two weights. Enhanced READ resolution is very important to make a memristive synapse functionally reliable. Usually, the READ resolution is very small for a memristive synapse with 4-bit data precision. This work considers a step-by-step analysis to enhance the READ current resolution for a current-controlled memristor-based synapse. An empirical model is used to characterize the HfO2-based memristive device. 1st and 2nd stage device of our proposed synapse can be scaled to enhance the READ current margin up to ~ 4.3x and ~ 21% respectively. Moreover, READ current resolution can be enhanced with run-time adaptation features such as READ voltage scaling and body biasing. The READ voltage scaling and body biasing can improve the READ current resolution by about 46% and 15% respectively. TENNLabs' neuromorphic computing framework is leveraged to evaluate the effect of READ current resolution on classification applications. Higher READ current resolution shows better accuracy than lower resolution with different percentages of read noise scenarios.

Explore related subjects

cs.ET

Keep this discovery

Explore connections, maps & timelines

BibTeXRIS

Hritom Das, Nishith N. Chakraborty, Catherine Schuman, Garrett S. Rose. 2023-06-23. Enhanced Read Resolution in Reconfigurable Memristive Synapses for Spiking Neural Networks. https://doi.org/10.1038/s41598-024-58947-2

Cite the original work for its findings. Save a collection to share your selection of sources.

KEEP EXPLORING

Related papers

arXiv2026

Whole-Blood Boundary Analysis of BioFET-Based ctDNA Detection for Intravascular Sensing in Intrabody Nanonetworks

Liquid biopsy can detect tumor-derived biomarkers such as circulating tumor DNA (ctDNA), but ultra-low-fraction assays remain costly, slow, and difficult to scale. This motivates interest in intravascular in vivo sensing in the context of intrabody nanonetworks, where nanosensors could support local biomarker monitoring. BioFET-based nanosensors are relevant here because they are label-free, highly miniaturizable, and have shown strong ctDNA sensitivity in controlled media. We examine whether this sensitivity still yields reliable ctDNA detection in whole blood using a reduced-order stochastic simulation model that links operating-point selection, Debye-screened charge transduction, stochastic finite-capacity binding, nonspecific adsorption, background fluctuations, and intrinsic electronic noise to blank-threshold detection. Monte Carlo evaluation with physiologically grounded parameters shows that short Debye length and several-nanometer charge-to-channel separation attenuate the current shift, while low-frequency noise and background fluctuations reduce the margin between target-present and blank responses. Under the tested quasi-static charge-gating regime, the simulated current shifts do not reliably exceed the blank-derived threshold at low ctDNA concentrations. The model therefore provides a whole-blood boundary analysis that identifies which interface configurations and operating conditions most strongly limit reliable BioFET-based intravascular ctDNA detection.

cs.ET↗
arXiv2026

Beyond HBM-on-GPU: Thermal Design Envelope for 3D Volumetric DRAM-on-GPU Integration

The scaling of GPUs for AI and HPC workloads is increasingly constrained by the capacity, bandwidth, and thermal limits of both 2.5D HBM-GPU and direct-stacked 3D HBM-on-GPU integration. This work establishes the thermal design envelope for 3D volumetric DRAM-on-GPU integration, in which vertically oriented DRAM dies and interleaved cooling cavities reshape heat flow and memory interfacing above the GPU. Using a package-level thermal model anchored to a consistent HBM-on-GPU baseline and driven by a realistic reticle-scale non-uniform GPU power map, we quantify the key parameters governing thermal feasibility. Stack height is the dominant limiter of peak temperature, while cooling-cavity conductivity shifts the feasible region, and mold insertion and stack orientation further modulate thermal behavior. A distributed memory-controller and network-on-chip tier introduces only a moderate thermal penalty. Although die-level parallelism increases bandwidth, the reduction in simulated training time saturates once execution becomes compute-bound. These results define a bounded co-design space across bandwidth, capacity, and thermal constraints for 3D volumetric DRAM-on-GPU integration.

cs.ET↗
arXiv2026

Droop-Aware Foundation Model Power Flow

This paper develops a droop-aware extension of the GridFM power systems foundation model, embedding droop gains and frequency/voltage deadband parameters as per-bus node features to enable control-aware AC power-flow analysis. Existing power-flow datasets encode only static electrical features, conflating operating points from qualitatively different control regimes; this work resolves that gap by exposing droop and deadband parameters as structured node features, with deadband discontinuities handled through a smooth tanh approximation that preserves solver differentiability. A transformer-based graph neural network is pre-trained on masked reconstruction and fine-tuned on the resulting control-aware datasets. The framework is validated against PSCAD electromagnetic-transient simulations on a two-bus system (0.11% maximum steady-state error) and cross-validated against an independent PyPower droop solver on the IEEE 24-bus RTS. On the 24-bus system the surrogate attains R2 = 0.9996 for active generation and 0.0015 p.u. voltage-magnitude RMSE; scalability is confirmed on the IEEE 300-bus system (0.0036 p.u. RMSE, R2 = 0.9841 for voltage magnitude across 299,700 predictions). A three-mode control study further shows that the deadband widens the control-error distribution while leaving total droop compensation unchanged, establishing deadband width as an actionable node-level design feature.

cs.ET↗