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arXiv · 2309.10082

Constructor algorithms for building unconventional computers able to solve NP-complete problems

Abstract

Nature often builds physical structures tailored for specific information processing tasks with computations encoded using diverse phenomena. These can sometimes outperform typical general-purpose computers. However, describing the construction and function of these unconventional computers is often challenging. Here, we address this by introducing constructor algorithms in the context of a robotic wire machine that can be programmed to build networks of connected wires in response to a problem and then act upon these to efficiently carry out a desired computation. We show how this approach can be used to solve the NP-complete Subset Sum Problem (SSP) and provide information about the number of solutions through changes in the voltages and currents measured across these networks. This work provides a foundation for building unconventional computers that encode information purely in the lengths and connections of electrically conductive wires. It also demonstrates the power of computing paradigms beyond digital logic and opens avenues to more fully harness the inherent computational capabilities of diverse physical, chemical and biological substrates.

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Tony McCaffrey, Thomas E. Gorochowski, Lee Spector. 2023-09-18. Constructor algorithms for building unconventional computers able to solve NP-complete problems. https://arxiv.org/abs/2309.10082

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