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arXiv · 2310.14049

Post-Layout Simulation Driven Analog Circuit Sizing

Xiaohan Gao·Haoyi Zhang·Siyuan Ye·Mingjie Liu·David Z. Pan·Linxiao Shen·Runsheng Wang·Yibo Lin·Ru Huang
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Abstract

Post-layout simulation provides accurate guidance for analog circuit design, but post-layout performance is hard to be directly optimized at early design stages. Prior work on analog circuit sizing often utilizes pre-layout simulation results as the optimization objective. In this work, we propose a post-layout-simulation-driven (post-simulation-driven for short) analog circuit sizing framework that directly optimizes the post-layout simulation performance. The framework integrates automated layout generation into the optimization loop of transistor sizing and leverages a coupled Bayesian optimization algorithm to search for the best post-simulation performance. Experimental results demonstrate that our framework can achieve over 20% better post-layout performance in competitive time than manual design and the method that only considers pre-layout optimization.

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Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang. 2023-10-21. Post-Layout Simulation Driven Analog Circuit Sizing. https://arxiv.org/abs/2310.14049

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