Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap

Abstract

Virtual Prototypes act as an executable specification model, offering a unified behavior reference model for SW and HW engineers. However, between the VP and the HW still exists a gap, as the step from an architectural level VP implementation on the Transaction Level Modeling to the Register Transfer Layer implementation is considerably big. Especially when a company wants to focus on their Unique Selling-Point, the HW Design Space Exploration and acceptance tests should start as early as possible. Traditionally, this can only start once the rest of the System-on-Chip is also implemented in the RTL. As SoCs consist of many common subsystems like processors, memories, and peripherals, this may impact the time-to-market considerably. This is avoidable, however: In this paper we propose a Hardware-in-the-Loop strategy that allows to bridge the gap between the VP and RTL design that empowers engineers to focus on their USP while leveraging an existing suite of TLM Intellectual Properties for the common base-system components. We show how VPs and partial RTL implementations of a SoC can be combined in a Hardware-in-the-Loop simulation environment utilizing Field-Programmable Gate Arrays. The proposed approach allows early DSE, validation, and verification of SoC subsystems, which bridges the TLM/RTL gap. We evaluate our approach with a lightweight implementation of the proposed protocol, and three case-studies with real-world peripherals and accelerators on HW. Furthermore, we assess the capabilities of our approach and offer practical considerations for engineers utilizing this HIL approach for SoC design; and finally propose further extensions that can boost the approach for specialized applications like high-performance accelerators and computation.