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arXiv · 2312.06004

Multiplier Optimization via E-Graph Rewriting

Andy Wanna·Samuel Coward·Theo Drane·George A. Constantinides·Miloš D. Ercegovac
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Abstract

Multiplier circuits account for significant resource usage in datapath-dominated circuit designs, and RTL designers continue to build bespoke hand-crafted multiplication arrays for their particular application. The construction of an optimized multiplier presents trade-offs between pre-processing to generate a smaller array and array reduction. A data structure known as an e-graph has recently been applied to datapath optimization, where the e-graph's ability to efficiently explore trade-offs has been shown to be crucial. We propose an e-graph based rewriting framework to construct optimized multiplier circuits. Such a framework can express alternative multiplier representations and generate customized circuit designs. We demonstrate that the proposed tool, which we call OptiMult, can reduce the latency of a squarer by up to 46% and reduce the latency of a standard multiplier by up to 9% when compared against logic synthesis instantiated components.

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Andy Wanna, Samuel Coward, Theo Drane, George A. Constantinides, Miloš D. Ercegovac. 2023-12-10. Multiplier Optimization via E-Graph Rewriting. https://arxiv.org/abs/2312.06004

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