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arXiv · 2312.16436

Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators

Jingwei Cai·Zuotong Wu·Sen Peng·Yuchen Wei·Zhanhong Tan·Guiming Shi·Mingyu Gao·Kaisheng Ma
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Abstract

Chiplet technology enables the integration of an increasing number of transistors on a single accelerator with higher yield in the post-Moore era, addressing the immense computational demands arising from rapid AI advancements. However, it also introduces more expensive packaging costs and costly Die-to-Die (D2D) interfaces, which require more area, consume higher power, and offer lower bandwidth than on-chip interconnects. Maximizing the benefits and minimizing the drawbacks of chiplet technology is crucial for developing large-scale DNN chiplet accelerators, which poses challenges to both architecture and mapping. Despite its importance in the post-Moore era, methods to address these challenges remain scarce.

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Jingwei Cai, Zuotong Wu, Sen Peng, Yuchen Wei, Zhanhong Tan, Guiming Shi, Mingyu Gao, Kaisheng Ma. 2023-12-27. Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators. https://arxiv.org/abs/2312.16436

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