Chiplets on Wheels: Review Paper on Holistic Chiplet Solutions for Autonomous Vehicles

Swathi Narashiman; Venkat A; Divyaratna Joshi; Deepak Sridhar; Harish Rajesh; Sanjay Sattva; Aniruddha S; Jayanth B; Varun Manjunath; Ragavendiran N

arXiv · 2406.00182

Chiplets on Wheels: Review Paper on Holistic Chiplet Solutions for Autonomous Vehicles

Swathi Narashiman·Venkat A·Divyaratna Joshi·Deepak Sridhar·Harish Rajesh·Sanjay Sattva·Aniruddha S·Jayanth B·Varun Manjunath·Ragavendiran N

View original source ↗Read source document ↗Export metadata ↓

Abstract

On the advent of the slow death of Moore's law, the silicon industry is moving towards a new era of chiplets. The automotive industry is experiencing a profound transformation towards software-defined vehicles, fueled by the surging demand for automotive compute chips, expected to reach 20-22 billion by 2030. High-performance compute (HPC) chips become instrumental in meeting the soaring demand for computational power. Various strategies, including centralized electrical and electronic architecture and the innovative Chiplet Systems, are under exploration. The latter, breaking down System-on-Chips (SoCs) into functional units, offers unparalleled customization and integration possibilities. The research accentuates the crucial open Chiplet ecosystem, fostering collaboration and enhancing supply chain resilience. In this paper, we address the unique challenges that arise when attempting to leverage chiplet-based architecture to design a holistic silicon solution for the automotive industry. We propose a throughput-oriented micro-architecture for ADAS and infotainment systems alongside a novel methodology to evaluate chiplet architectures. Further, we develop in-house simulation tools leveraging the gem5 framework to simulate latency and throughput. Finally, we perform an extensive design of thermally-aware chiplet placement and develop a micro-fluids-based cooling design.

Explore related subjects

cs.AR

Keep this discovery

Explore connections, maps & timelines

BibTeX RIS

Swathi Narashiman, Venkat A, Divyaratna Joshi, Deepak Sridhar, Harish Rajesh, Sanjay Sattva, Aniruddha S, Jayanth B, Varun Manjunath, Ragavendiran N. 2024-05-31. Chiplets on Wheels: Review Paper on Holistic Chiplet Solutions for Autonomous Vehicles. https://arxiv.org/abs/2406.00182

Cite the original work for its findings. Save a collection to share your selection of sources.

KEEP EXPLORING

Related papers

arXiv2026

Bi-SamplerZ: A Rejection-Aware Cooperative Gaussian Sampling Framework for Falcon Signature Hardware

We present Bi-SamplerZ, a rejection-aware cooperative sampling framework that converts this idle capacity into useful computation. After an asymmetric accept/reject outcome, Bi- SamplerZ latches the completed logical result and dynamically reassigns the released physical datapath to the unfinished target. The two paths then evaluate fresh independent candidates for the same remaining distribution. We show that this post-rejection cooperation increases the assisted-round completion probability without modifying the underlying candidate distribution or Bernoulli acceptance rule, and we state the randomness-allocation conditions required to preserve the joint output distribution of the original pair of logical sampler calls

cs.AR↗

arXiv2026

A Multi-Engine Dataflow for MoE Decoding on Scratchpad-Based Tensor Accelerators

Mixture-of-Experts (MoE) decoding on scratchpad-based tensor accelerators (STA) is dominated by moving expert weights while the compute engines sit idle. This traffic is hard to hide, because the experts are known only after routing, and hard to shrink without losing quality or adding critical-path work. We present CARDAN, which represents each expert-weight matrix as a vector-quantized component plus a shared-basis low-rank component and co-designs this representation with a multi-engine decoding dataflow. The representation separates expert-common from expert-private work, so the dataflow overlaps DMA with computation on several engines. Across five MoE families on AWS Trainium3, CARDAN matches or improves BF16-teacher perplexity across all five models and speeds up batch-one decoding by 1.15-1.31x over AWS dense MoE megakernels, rising to 1.7x at batch size 16.

cs.AR↗

arXiv2026

Dissecting How Die Scaling Breaks GPU Fine-grained Scheduling

Modern GPUs are no longer physically symmetric. Die scaling leads to both manufacturing-driven floorsweeping and cache and memory partitioning. The former creates chip-specific compute topologies, while the latter causes non-uniform memory access. These asymmetries are substantial. Topology-oblivious compute unit allocation can lead to up to 1.33x performance variation, while remote accesses increase HBM latency by up to 67% and nearly double L2 latency. However, these asymmetries are hidden behind the GPU's logical resource abstractions and can vary across chips. We develop lightweight characterization methods to uncover per-chip compute topology and memory affinity. We then use the discovered information to make existing fine-grained scheduling asymmetry-aware, considering not only how many resources are allocated but also which physical resources are assigned. Across full-GPU kernel execution, intra-application multiplexing, and inter-application co-location, asymmetry-aware scheduling improves mainstream kernels by up to 1.22x, multiplexed LLM inference by up to 14.3%, and avoids up to 1.33x performance variation.

cs.AR↗