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arXiv · 2406.02406

Demonstration of two-dimensional connectivity for a scalable error-corrected ion-trap quantum processor architecture

Abstract

A major hurdle for building a large-scale quantum computer is increasing the number of qubits while maintaining connectivity between them. In trapped-ion devices, this connectivity can be achieved by moving subregisters consisting of a few ions across the processor. Here, we focus on an architecture, which we refer to as the Quantum Spring Array (QSA), that is based on a rectangular two-dimensional lattice of linear strings of ions. Connectivity between adjacent ion strings can be controlled by adjusting their separation. This requires control of trapping potentials along two directions, one along the axis of the ion string and one radial to it. In this work, we investigate key elements of the QSA architecture along both directions: We show that the coupling rate between neighboring lattice sites increases with the number of ions per site and the motion of the coupled system can be resilient to electrical noise, both being key requisites for fast and high-fidelity quantum gate operations. The coherence of the coupling is assessed and an entangling gate between qubits stored in radially separated trapping regions is demonstrated. Moreover, we demonstrate control over radio-frequency signals to adjust the radial separation, and thus the coupling rate, between strings. We further present constructions for the implementation of parallelized, transversal gate operations, and map the QSA architecture to code primitives for fault-tolerant quantum error correction, providing a step towards a quantum processor architecture that is optimized for large-scale operation.

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BibTeXRIS

Marco Valentini, Martin W. van Mourik, Friederike Butt, Jakob Wahl, Matthias Dietl, Michael Pfeifer, Fabian Anmasser, Yves Colombe, Clemens Rössler, Philip Holz, Rainer Blatt, Alejandro Bermudez, Markus Müller, Thomas Monz, Philipp Schindler. 2024-06-04. Demonstration of two-dimensional connectivity for a scalable error-corrected ion-trap quantum processor architecture. https://doi.org/10.1103/b9s1-6r44

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