A 1.8-um pitch, 47-ps jitter SPAD Array in 130nm SiGe BiCMOS Process

Feng Liu; Edoardo Charbon

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arXiv · 2406.13686

A 1.8-um pitch, 47-ps jitter SPAD Array in 130nm SiGe BiCMOS Process

Feng Liu·Edoardo Charbon

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Abstract

We introduce the world's first SPAD family design in 130 nm SiGe BiCMOS process. At 1.8um, we achieved the smallest pitch on record thanks to guard-ring sharing techniques, while keeping a relatively high fill factor of 24.2%. 4x4 SPAD arrays with two parallel selective readout circuits were designed to explore crosstalk and scalability. The SPAD family has a minimum breakdown voltage of 11 V, a maximum PDP of 40.6% and a typical timing jitter of 47 ps FWHM. The development of silicon SPADs in SiGe process paves the way to Ge-on-Si SPADs for SWIR applications, and to cryogenic optical interfaces for quantum applications.

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Feng Liu, Edoardo Charbon. 2024-06-19. A 1.8-um pitch, 47-ps jitter SPAD Array in 130nm SiGe BiCMOS Process. https://arxiv.org/abs/2406.13686

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