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arXiv · 2408.06935

UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators

Abstract

Multipliers and multiply-accumulators (MACs) are critical arithmetic circuit components in the modern era. As essential components of AI accelerators, they significantly influence the area and performance of compute-intensive circuits. This paper presents UFO-MAC, a unified framework for the optimization of multipliers and MACs. Specifically, UFO-MAC employs an optimal compressor tree structure and utilizes integer linear programming (ILP) to refine the stage assignment and interconnection of the compressors. Additionally, it explicitly exploits the non-uniform arrival time profile of the carry propagate adder (CPA) within multipliers to achieve targeted optimization. Moreover, the framework also supports the optimization of fused MAC architectures. Experimental results demonstrate that multipliers and MACs optimized by UFO-MAC Pareto-dominate state-of-the-art baselines and commercial IP libraries. The performance gain of UFO-MAC is further validated through the implementation of multipliers and MACs within functional modules, underlining its efficacy in real scenarios.

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Dongsheng Zuo, Jiadong Zhu, Chenglin Li, Yuzhe Ma. 2024-08-13. UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators. https://arxiv.org/abs/2408.06935

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