The nature of silicon PN junction impedance at high frequency

Abstract

A thorough understanding of the small-signal response of solar cells can reveal intrinsic device characteristics and pave the way for innovations. This study investigates the impedance of crystalline silicon PN junction devices using TCAD simulations, focusing on the impact of frequency, bias voltage, and the presence of a low-high (LH) junction. It is shown that the PN junction exhibits a fixed $RC$-loop behavior at low frequencies, but undergoes relaxation in both resistance $R_j$ and capacitance $C_j$ as frequency increases. Moreover, it is revealed that the addition of a LH junction impacts the impedance by altering $R_j$, $C_j$, and the series resistance $R_s$. Contrary to conventional modeling approaches, which often include an additional $RC$-loop to represent the LH junction, this study suggests that such a representation does not represent the underlying physics, particularly the frequency-dependent behavior of $R_j$ and $C_j$.