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arXiv · 2409.20506

Nanosecond hardware regression trees in FPGA at the LHC

Pavel Serhiayenka·Stephen Roche·Benjamin Carlson·Tae Min Hong
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Abstract

We present a generic parallel implementation of the decision tree-based machine learning (ML) method in hardware description language (HDL) on field programmable gate arrays (FPGA). A regression problem in high energy physics at the Large Hadron Collider is considered: the estimation of the magnitude of missing transverse momentum using boosted decision trees (BDT). A forest of twenty decision trees each with a maximum depth of ten using eight input variables of 16-bit precision is executed with a latency of less than 10 ns using O(0.1%) resources on Xilinx UltraScale+ VU9P -- approximately ten times faster and five times smaller compared to similar designs using high level synthesis (HLS) -- without the use of digital signal processors (DSP) while eliminating the use of block RAM (BRAM). We also demonstrate a potential application in the estimation of muon momentum for ATLAS RPC at HL-LHC.

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Pavel Serhiayenka, Stephen Roche, Benjamin Carlson, Tae Min Hong. 2024-09-30. Nanosecond hardware regression trees in FPGA at the LHC. https://doi.org/10.1016/j.nima.2025.170209

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