Scaling Effects of Transistor Leakage Current and IR Drop on 1T1R Memory Arrays

Abstract

1T1R (1-transistor-1-resistor) memory crossbar arrays represent a promising solution for compute-in-memory matrix-vector multiplication accelerators and embedded or storage-class memory. However, the size and scaling of these arrays are hindered by critical challenges, such as the IR drop on metal lines and the accumulation of leakage current from the transistors. Although the IR drop issue has been extensively investigated, the impact of transistor leakage current has received limited attention. In this work, we investigate both issues and highlight how transistor leakage in 1T1R arrays has effects similar to IR drop, which degrades the memory cell sensing margin, especially as the technology node scales down. This degradation could pose reliability concerns, particularly where the on/off ratio or sensing margin of memristors is critical. We characterized the joint effects of transistor read resistance, transistor leakage current, and IR drop as the array size scales up and the fabrication node scales down. Based on a model developed using specifications of a 22nm FDSOI technology, we found that an optimal resistance range of memristors exists for good array scaling capability, where the transistor read resistance and the IR drop issue establish a lower resistance boundary, while the transistor leakage issue sets an upper resistance boundary. This work provides valuable scaling guidelines for engineering the properties of memristor devices in 1T1R memory arrays.