Optimized Cryo-CMOS Technology with VTH<0.2V and Ion>1.2mA/um for High-Peformance Computing

Chang He; Yue Xin; Longfei Yang; Zewei Wang; Zhidong Tang; Xin Luo; Renhe Chen; Zirui Wang; Shuai Kong; Jianli Wang; Jianshi Tang; Xiaoxu Kang; Shoumian Chen; Yuhang Zhao; Shaojian Hu; Xufeng Kou

arXiv · 2411.03099

Optimized Cryo-CMOS Technology with VTH<0.2V and Ion>1.2mA/um for High-Peformance Computing

Chang He·Yue Xin·Longfei Yang·Zewei Wang·Zhidong Tang·Xin Luo·Renhe Chen·Zirui Wang·Shuai Kong·Jianli Wang·Jianshi Tang·Xiaoxu Kang·Shoumian Chen·Yuhang Zhao·Shaojian Hu·Xufeng Kou

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Abstract

We report the design-technology co-optimization (DTCO) scheme to develop a 28-nm cryogenic CMOS (Cryo-CMOS) technology for high-performance computing (HPC). The precise adjustment of halo implants manages to compensate the threshold voltage (VTH) shift at low temperatures. The optimized NMOS and PMOS transistors, featured by VTH<0.2V, sub-threshold swing (SS)<30 mV/dec, and on-state current (Ion)>1.2mA/um at 77K, warrant a reliable sub-0.6V operation. Moreover, the enhanced driving strength of Cryo-CMOS inherited from a higher transconductance leads to marked improvements in elevating the ring oscillator frequency by 20%, while reducing the power consumption of the compute-intensive cryogenic IC system by 37% at 77K.

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Chang He, Yue Xin, Longfei Yang, Zewei Wang, Zhidong Tang, Xin Luo, Renhe Chen, Zirui Wang, Shuai Kong, Jianli Wang, Jianshi Tang, Xiaoxu Kang, Shoumian Chen, Yuhang Zhao, Shaojian Hu, Xufeng Kou. 2024-11-05. Optimized Cryo-CMOS Technology with VTH<0.2V and Ion>1.2mA/um for High-Peformance Computing. https://arxiv.org/abs/2411.03099

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