Fused-MemBrain: a spiking processor combining CMOS and self-assembled memristive networks

Davide Cipollini; Hugh Greatorex; Michele Mastella; Elisabetta Chicca; Lambert Schomaker

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arXiv · 2411.19353

Fused-MemBrain: a spiking processor combining CMOS and self-assembled memristive networks

Davide Cipollini·Hugh Greatorex·Michele Mastella·Elisabetta Chicca·Lambert Schomaker

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Abstract

In an era characterized by the rapid growth of data processing, developing new and efficient data processing technologies has become a priority. We address this by proposing a novel type of neuromorphic technology we call Fused-MemBrain. Our proposal is inspired by Golgi's theory modeling the brain as a syncytial continuum, in contrast to Cajal's theory of neurons and synapses being discrete elements. While Cajal's theory has long been the dominant and experimentally validated view of the nervous system, recent discoveries showed that a species of marine invertebrate (ctenophore Mnemiopsis leidyi) may be better described by Golgi's theory. The core idea is to develop hardware that functions analogously to a syncytial network, exploiting self-assembled memristive systems and combining them with CMOS technologies, interfacing with the silicon back-end-of-line. In this way, a memristive self-assembled material can cheaply and efficiently replace the synaptic connections between CMOS neuron implementations in neuromorphic hardware, enhancing the capability of massively parallel computation. The fusion of CMOS circuits with a memristive ``plexus'' allows information transfer without requiring engineered synapses, which typically consume significant area. As the first step toward this ambitious goal, we present a simulation of a memristive network interfaced with spiking neural networks. Additionally, we describe the potential benefits of such a system, along with key technical aspects it should incorporate.

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Davide Cipollini, Hugh Greatorex, Michele Mastella, Elisabetta Chicca, Lambert Schomaker. 2024-11-28. Fused-MemBrain: a spiking processor combining CMOS and self-assembled memristive networks. https://arxiv.org/abs/2411.19353

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