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arXiv · 2412.17536

FPGA Implementation of Low-Power Multiplierless Pre-Processing Free Chromatic Dispersion Equalizer

Geraldo Gomes·Pedro Freire·Jaroslaw E. Prilepsky·Sergei K. Turitsyn
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Abstract

We present a novel time-domain chromatic dispersion equalizer, implemented on FPGA, eliminating pre-processing and multipliers, achieving up to 54.3% energy savings over 80-1280 km with a simple, low-power design.

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Geraldo Gomes, Pedro Freire, Jaroslaw E. Prilepsky, Sergei K. Turitsyn. 2024-12-23. FPGA Implementation of Low-Power Multiplierless Pre-Processing Free Chromatic Dispersion Equalizer. https://arxiv.org/abs/2412.17536

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