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arXiv · 2502.02065

Hardware and software build flow with SoCMake

Risto Pejašinović·Alessandro Caratelli·Anvesh Nookala·Benoît Walter Denkinger·Marco Andorno
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Abstract

The increasing demand for electronics is driving shorter development cycles for application-specific integrated circuits (ASICs). To meet these constraints, hardware designers emphasize reusability and modularity of IP blocks, leveraging standard system-on-chip (SoC) architectures with integrated processors and common interconnects. While these architectures reduce design and verification efforts, they also introduce complexity, as verification must encompass both hardware and software execution. To enhance reusability, hardware IP blocks are often described in higher-abstraction-level languages such as Chisel and SystemRDL, relying on compilers to generate Verilog for RTL simulation and implementation. At the system level, SoC modeling and verification leverage C++ and SystemC, underscoring the need for software compilation. Consequently, an effective build system must support both hardware design flows and software compilation, including cross-compilation for C++, C, and assembly. Existing hardware build systems lack sufficient support for software compilation, necessitating the development of a new solution. In response, the Microelectronics section of CERN initiated SoCMake, initially as part of the System-on-Chip Radiation Tolerant Ecosystem (SOCRATES). Designed to automate the generation of fault-tolerant RISC-V SoCs for high-energy physics environments, SoCMake has since evolved into a generic open-source build tool for SoC generation.

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Risto Pejašinović, Alessandro Caratelli, Anvesh Nookala, Benoît Walter Denkinger, Marco Andorno. 2025-02-04. Hardware and software build flow with SoCMake. https://arxiv.org/abs/2502.02065

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