DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining

Sungyoung Lee; Ziyi Wang; Seunggeun Kim; Taekyun Lee; Yao Lai; David Z. Pan

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arXiv · 2502.08949

DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining

Sungyoung Lee·Ziyi Wang·Seunggeun Kim·Taekyun Lee·Yao Lai·David Z. Pan

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Abstract

Pretraining models with unsupervised graph representation learning has led to significant advancements in domains such as social network analysis, molecular design, and electronic design automation (EDA). However, prior work in EDA has mainly focused on pretraining models for digital circuits, overlooking analog and mixed-signal circuits. To bridge this gap, we introduce DICE, a Device-level Integrated Circuits Encoder, which is the first graph neural network (GNN) pretrained via self-supervised learning specifically tailored for graph-level prediction tasks in both analog and digital circuits. DICE adopts a simulation-free pretraining approach based on graph contrastive learning, leveraging two novel graph augmentation techniques. Experimental results demonstrate substantial performance improvements across three downstream tasks, highlighting the effectiveness of DICE for both analog and digital circuits. The code is available at github.com/brianlsy98/DICE.

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Sungyoung Lee, Ziyi Wang, Seunggeun Kim, Taekyun Lee, Yao Lai, David Z. Pan. 2025-05-19. DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining. https://arxiv.org/abs/2502.08949

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