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arXiv · 2503.19770

Brain Organoid Computing -- an Overview

Abstract

The aim of this paper is to give an overview of brain organoid computing, its characteristics, challenges, as well as possible advantages for future applications in the field of artificial intelligence. An important part is the extensive bibliography covering all relevant aspects and questions on this topic. Brain organoids - three-dimensional in vitro neural structures derived from human stem cells - have recently garnered attention not only in medical research but also as potential substrates for unconventional computing. Their biological nature allows them to exhibit learning behavior, plasticity, and parallel information processing, making them fundamentally different from traditional silicon-based systems. This opens up new perspectives on how intelligent systems might be designed in the future. Using brain organoids for computing presents a possible pathway towards more adaptive, energy-efficient, and biologically inspired forms of AI. However, challenges persist, particularly regarding lifespan, interfacing, reproducibility, and ethical concerns regarding the use of human-derived tissue. This paper aims to provide a foundational understanding for researchers exploring the convergence of human biology and computation.

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Yannic Talavera, Bernd Ulmann. 2025-11-03. Brain Organoid Computing -- an Overview. https://arxiv.org/abs/2503.19770

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