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arXiv · 2506.11270

Drift-resilient mid-circuit measurement and state preparation error mitigation for dynamic circuits

Abstract

Quantum error mitigation (QEM) for dynamic circuits, i.e., those incorporating mid-circuit measurements and feedforward, is important for two key reasons. First, quantum error correction (QEC) circuits are instances of dynamic circuits, and therefore a dynamic circuit-compatible QEM can extend circuit depth and address errors that QEC struggles with. Second, recent studies show that dynamic circuits can significantly outperform purely unitary ones. However, mid-circuit measurement errors remain a major bottleneck. Current solutions rely on readout noise characterization that is vulnerable to temporal noise drifts. To the best of our knowledge, no readout mitigation schemes are resilient to temporal noise drifts. By introducing parity-based noise amplification in repeated measurements, we derive and experimentally demonstrate a drift-resilient protocol for addressing preparation, mid-circuit, and terminating measurement errors without requiring calibration or characterization. Drift resilience increases the longest possible execution time (in terms of shots) and enables flexibility by combining data from non-consecutive times. For platforms such as trapped ions, where the measurements are highly disruptive, we provide an alternative reset-based mitigation scheme. We demonstrate our methods experimentally on IBMQ and Quantinuum hardware. Combined with the Layered-KIK gate error mitigation protocol, the presented readout mitigation approach enables "End-to-end" mitigation for dynamic circuits, that can improve the outcomes of QEC experiments, and that covers the widest range of errors to the best of our knowledge. Other applications of the presented methods include a faster alternative to gate-set tomography and diagnostics of defective qubits during the execution of the target algorithm.

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BibTeXRIS

Jader P. Santos, Raam Uzdin. 2025-09-03. Drift-resilient mid-circuit measurement and state preparation error mitigation for dynamic circuits. https://arxiv.org/abs/2506.11270

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