Development and testing of integrated readout electronics for next generation SiSeRO (Single electron Sensitive Read Out) devices

Abstract

The first generation of Single electron Sensitive Read Out (SiSeRO) amplifiers, employed as on-chip charge detectors for charge-coupled devices (CCDs) have demonstrated excellent noise and spectral performance: a responsivity of around 800 pA per electron, an equivalent noise charge (ENC) of 3.2 electrons root mean square (RMS), and a full width half maximum (FWHM) energy resolution of 130 eV at 5.9 keV for a readout speed of 625 Kpixel/s. Repetitive Non Destructive Readout (RNDR) has also been demonstrated with these devices, achieving an improved ENC performance of 0.36 electrons RMS after 200 RNDR cycles. In order to mature this technology further, Stanford University, in collaboration with MIT Kavli Institute and MIT Lincoln Laboratory, are developing new SiSeRO detectors with improved geometries that should enable greater responsivity and improved noise performance. These include CCD devices employing arrays of SiSeRO amplifiers to optimize high speed, low noise RNDR readout and a proof-of-concept SiSeRO active pixel sensor (APS). To read out these devices, our team has developed a compact, 8-channel, fast, low noise, low power application specific integrated circuit (ASIC) denoted the Multi-Channel Readout Chip (MCRC) that includes an experimental drain current readout mode intended for SiSeRO devices. In this paper, we present results from the first tests of SiSeRO CCD devices operating with MCRC readout, and our designs for next generation SiSeRO devices.