Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication

Pragun Jaswal; L. Hemanth Krishna; B. Srinivasu

doi:10.1109/vlsid68508.2026.00103

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arXiv · 2509.00778

Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication

Pragun Jaswal·L. Hemanth Krishna·B. Srinivasu

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Abstract

Deep Neural Networks (DNNs) require highly efficient matrix multiplication engines for complex computations. This paper presents a systolic array architecture incorporating novel exact and approximate processing elements (PEs), designed using energy-efficient positive partial product and negative partial product cells, termed as PPC and NPPC, respectively. The proposed 8-bit exact and approximate PE designs are employed in a 8x8 systolic array, which achieves a energy savings of 22% and 32%, respectively, compared to the existing design. To demonstrate their effectiveness, the proposed PEs are integrated into a systolic array (SA) for Discrete Cosine Transform (DCT) computation, achieving high output quality with a PSNR of 38.21,dB. Furthermore, in an edge detection application using convolution, the approximate PE achieves a PSNR of 30.45,dB. These results highlight the potential of the proposed design to deliver significant energy efficiency while maintaining competitive output quality, making it well-suited for error-resilient image and vision processing applications.

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Pragun Jaswal, L. Hemanth Krishna, B. Srinivasu. 2026-01-28. Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication. https://doi.org/10.1109/vlsid68508.2026.00103

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