The Post-Silicon Semiconductor Era: A Review of Physics, Synthesis, and Architectural Integration of Carbon Nanotube Field-Effect Transistors

Abstract

Silicon CMOS scaling is approaching a set of hard physical limits. Direct source-to-drain quantum tunneling, subthreshold swing degradation, and the Dark Silicon thermal ceiling motivate the search for a new channel material. This review builds the case for single-walled carbon nanotubes (SWCNTs) as that material. We follow a continuous narrative from electronic structure theory through synthesis to integration. The SWCNT bandgap and near-ballistic transport limits are derived from the graphene zone-folding framework and Landauer-Büttiker formalism. We benchmark these theoretical limits against ideal coaxial electrostatic bounds to evaluate how the geometry suppresses short-channel effects before tunneling dominates. Comparing this framework against 5 nm experimental data illustrates the aggressive subthreshold degradation driven by source-to-drain tunneling. Furthermore, we derive the exact areal-density equivalence between 1D and 2D quantum capacitance. This demonstrates that close-packed arrays cannot close the dimensional gap to 2D materials, underscoring why superior carrier velocity and electrostatics must carry the CNTFET advantage. Next, we examine CoMoCAT growth and aqueous two-phase extraction against logic fabrication purity demands alongside contact engineering and doping. A closing techno-economic analysis weighs this picture against IEEE IRDS projections. Ultimately, materials purification, contact reliability, and bias temperature instability remain the practical barriers to commercial adoption.