FPGA-Based RoCEv2-RDMA Readout Electronics for the CTAO-LST Advanced Camera

Abstract

CTAO's (Cherenkov Telescope Array Observatory) largest telescopes type, the LST (Large-Sized Telescope), are being installed at the northern site of the Cherenkov Telescope Array (CTA) at the Observatorio del Roque de los Muchachos on the Canary island of La Palma. Their aim is to capture the lowest-energy gamma rays of the observatory. The hereby proposed readout electronics architecture, serving as a proof-of-concept for its advanced camera upgrade, relies on a custom high-channel count fast sampling hardware digitizer board acting as a Front-End. The design includes a versatile pre-amplification stage and high-speed serial links for streaming JESD204C-compliant data at rates approaching 12 Gb/s per lane. The data get transferred to Back-End electronics for a first data-processing and trigger before being transmitted to event-building servers through 10 Gb/s Ethernet links. The performance of the link is exploited by implementing RDMA communication in hardware, thanks to a RoCEv2 core written in Bluespec SystemVerilog, enabling the possibility of transfer data directly to processing units without CPU intervention. Hardware design and characterization of the Front End board are reported, as well as a detailed description and tests of the Back End RDMA firmware.