Search arXivSearch

arXiv · 2509.26065

Runtime Energy Monitoring for RISC-V Soft-Cores

Abstract

Energy efficiency is one of the major concern in designing advanced computing infrastructures. From single nodes to large-scale systems (data centers), monitoring the energy consumption of the computing system when applications run is a critical task. Designers and application developers often rely on software tools and detailed architectural models to extract meaningful information and determine the system energy consumption. However, when a design space exploration is required, designers may incur in continuous tuning of the models to match with the system under evaluation. To overcome such limitations, we propose a holistic approach to monitor energy consumption at runtime without the need of running complex (micro-)architectural models. Our approach is based on a measurement board coupled with a FPGA-based System-on-Module. The measuring board captures currents and voltages (up to tens measuring points) driving the FPGA and exposes such values through a specific memory region. A running service reads and computes energy consumption statistics without consuming extra resources on the FPGA device. Our approach is also scalable to monitoring of multi-nodes infrastructures (clusters). We aim to leverage this framework to perform experiments in the context of an aeronautical design application; specifically, we will look at optimizing performance and energy consumption of a shallow artificial neural network on RISC-V based soft-cores.

Explore related subjects

Keep this discovery

Explore connections, maps & timelines

BibTeXRIS

Alberto Scionti, Paolo Savio, Francesco Lubrano, Olivier Terzo, Marco Ferretti, Florin Apopei, Juri Bellucci, Ennio Spano, Luca Carriere. 2025-09-30. Runtime Energy Monitoring for RISC-V Soft-Cores. https://arxiv.org/abs/2509.26065

Cite the original work for its findings. Save a collection to share your selection of sources.

KEEP EXPLORING

Related papers

Bi-SamplerZ: A Rejection-Aware Cooperative Gaussian Sampling Framework for Falcon Signature Hardware

We present Bi-SamplerZ, a rejection-aware cooperative sampling framework that converts this idle capacity into useful computation. After an asymmetric accept/reject outcome, Bi- SamplerZ latches the completed logical result and dynamically reassigns the released physical datapath to the unfinished target. The two paths then evaluate fresh independent candidates for the same remaining distribution. We show that this post-rejection cooperation increases the assisted-round completion probability without modifying the underlying candidate distribution or Bernoulli acceptance rule, and we state the randomness-allocation conditions required to preserve the joint output distribution of the original pair of logical sampler calls

cs.AR

A Multi-Engine Dataflow for MoE Decoding on Scratchpad-Based Tensor Accelerators

Mixture-of-Experts (MoE) decoding on scratchpad-based tensor accelerators (STA) is dominated by moving expert weights while the compute engines sit idle. This traffic is hard to hide, because the experts are known only after routing, and hard to shrink without losing quality or adding critical-path work. We present CARDAN, which represents each expert-weight matrix as a vector-quantized component plus a shared-basis low-rank component and co-designs this representation with a multi-engine decoding dataflow. The representation separates expert-common from expert-private work, so the dataflow overlaps DMA with computation on several engines. Across five MoE families on AWS Trainium3, CARDAN matches or improves BF16-teacher perplexity across all five models and speeds up batch-one decoding by 1.15-1.31x over AWS dense MoE megakernels, rising to 1.7x at batch size 16.

cs.AR

Dissecting How Die Scaling Breaks GPU Fine-grained Scheduling

Modern GPUs are no longer physically symmetric. Die scaling leads to both manufacturing-driven floorsweeping and cache and memory partitioning. The former creates chip-specific compute topologies, while the latter causes non-uniform memory access. These asymmetries are substantial. Topology-oblivious compute unit allocation can lead to up to 1.33x performance variation, while remote accesses increase HBM latency by up to 67% and nearly double L2 latency. However, these asymmetries are hidden behind the GPU's logical resource abstractions and can vary across chips. We develop lightweight characterization methods to uncover per-chip compute topology and memory affinity. We then use the discovered information to make existing fine-grained scheduling asymmetry-aware, considering not only how many resources are allocated but also which physical resources are assigned. Across full-GPU kernel execution, intra-application multiplexing, and inter-application co-location, asymmetry-aware scheduling improves mainstream kernels by up to 1.22x, multiplexed LLM inference by up to 14.3%, and avoids up to 1.33x performance variation.

cs.AR