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arXiv · 2510.22674

Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications

L. Hemanth Krishna·Srinivasu Bodapati·Sreehari Veeramachaneni·BhaskaraRao Jammu·Noor Mahammad Sk
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Abstract

This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two types of sign-focused compressors: A + B + C + 1 and A + B + C + D + 1. Both exact and approximate compressor designs are utilized, with a focus on efficiently handling constant value "1" and negative partial products, which frequently appear in the partial product matrices of signed multipliers. To further enhance efficiency, the lower N - 1 columns of the partial product matrix are truncated, followed by an error compensation mechanism. Experimental results show that the proposed 8-bit approximate multiplier achieves a 29.21% reduction in power delay product (PDP) and a 14.39% reduction in power compared to the best of existing multipliers. The proposed multiplier is integrated into a custom convolution layer and performs edge detection, demonstrating its practical utility in real-world applications.

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L. Hemanth Krishna, Srinivasu Bodapati, Sreehari Veeramachaneni, BhaskaraRao Jammu, Noor Mahammad Sk. 2025-10-26. Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications. https://arxiv.org/abs/2510.22674

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