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arXiv · 2601.03976

On-Device Deep Reinforcement Learning for Decentralized Task Offloading Performance trade-offs in the training process

Abstract

Allowing less capable devices to offload computational tasks to more powerful devices or servers enables the development of new applications that may not run correctly on the device itself. Deciding where and why to run each of those applications is a complex task. Therefore, different approaches have been adopted to make offloading decisions. In this work, we propose a decentralized Deep Reinforcement Learning (DRL) agent to address the selection of computing locations. Unlike most existing work, we analyze it in a real testbed composed of various edge devices running the agent to determine where to execute each task. These devices are connected to a Multi-Access Edge Computing (MEC) server and a Cloud server through 5G communications. We evaluate not only the agent's performance in meeting task requirements but also the implications of running this type of agent locally, assessing the trade-offs of training locally versus remotely in terms of latency and energy consumption.

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BibTeXRIS

Gorka Nieto, Idoia de la Iglesia, Cristina Perfecto, Unai Lopez-Novoa. 2026-01-07. On-Device Deep Reinforcement Learning for Decentralized Task Offloading Performance trade-offs in the training process. https://arxiv.org/abs/2601.03976

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