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arXiv · 2601.08099

Directional Electrical Spiking, Bursting, and Information Propagation in Oyster Mycelium Recorded with a Star-Shaped Electrode Array

Abstract

Electrical activity in fungal mycelium has been reported in numerous species and experimental contexts, yet its spatial organisation and propagation remain insufficiently characterised. In this study we investigate the spatiotemporal structure of electrical potential dynamics in oyster mushroom (\textit{Pleurotus ostreatus}) mycelium colonising a wood-shavings substrate. Electrical signals were recorded using an eight-channel star-shaped differential electrode array providing angular resolution around a central region of colonised substrate. We analyse spike statistics, bursting behaviour, inter-channel correlations, and event-based propagation delays. The results reveal strong directional heterogeneity in spiking frequency and amplitude, clustered bursting dynamics, partial and localised coupling between channels, and reproducible propagation patterns across spatial sectors. Electrical bursts originate preferentially in specific directions and recruit other regions with with characteristic delays ranging from seconds to minutes to hours. These findings support the interpretation of fungal mycelium as a spatially extended excitable medium capable of slow, distributed electrical signalling and signal integration.

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Andrew Adamatzky. 2026-01-13. Directional Electrical Spiking, Bursting, and Information Propagation in Oyster Mycelium Recorded with a Star-Shaped Electrode Array. https://arxiv.org/abs/2601.08099

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