Dissipation-Reliability Tradeoff for Stochastic CMOS Bits in Series

Abstract

Physical instantiations of a bit of information are subject to thermal noise that can trigger unintended bit-flip errors. Bits implemented with CMOS technology typically operate in regimes that reliably suppress these errors with a large supply voltage, but miniaturization and circuit design for implantable biomedical devices motivate error suppression via alternative low-voltage strategies. We present and analyze an error-suppression technique that involves coupling multiple CMOS units into chains, introducing a natural error correction arising from inter-unit correlations. Using tensor networks to numerically solve a stochastic master equation for the CMOS chain, we quantify the dissipation-reliability tradeoff across system sizes that would be intractable with conventional sparse-matrix methods. The calculations show that the typical time for bit-flip errors grows exponentially in the square of the supply voltage but subexponentially with the chain length, a scaling we attribute to a spatially localized, domain-wall-mediated flip rather than a coherent one. While a CMOS chain adds stability compared to a single CMOS unit for a fixed low supply voltage, increasing the supply voltage is a lower-dissipation route to equivalent stability.