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arXiv · 2603.15095

Synergizing a Decentralized Framework with LLM-Assisted Skill and Willingness-Aware Task Assignment for Volunteer Crowdsourcing

Abstract

Volunteer crowdsourcing or VCS platforms increasingly support education, healthcare, disaster response, and smart city applications, yet assigning volunteers to complex tasks remains challenging due to fine-grained skill heterogeneity, unstructured profiles, dynamic willingness, and bursty workloads. Existing methods often rely on coarse or keyword-based skill representations, resulting in poor matching quality. We propose a hybrid VCS framework that integrates LLM-assisted semantic preprocessing, an interpretable skill- and willingness-aware assignment engine, and blockchain-enforced execution. The LLM is used only to extract and canonicalize fine-grained skills and preference cues from unstructured resumes and task descriptions, while assignment is performed by a utility-driven matcher that models partial skill coverage and participation likelihood. Smart contracts provide transparent and tamper-resistant enforcement without on-chain optimization overhead. Experiments on diverse resume datasets show a 42.3% improvement in assignment utility over skill-only greedy matching and an increase in task coverage from 0.80 to 0.90. These results highlight the value of combining semantic intelligence, interpretable matching, and decentralized enforcement for effective volunteer-task allocation.

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BibTeXRIS

Riya Samanta, Rituparna Bhattyacharya. 2026-03-16. Synergizing a Decentralized Framework with LLM-Assisted Skill and Willingness-Aware Task Assignment for Volunteer Crowdsourcing. https://arxiv.org/abs/2603.15095

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